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19 lines
312 B
Verilog
19 lines
312 B
Verilog
module dlatchn(input ENA, D, output reg Q, output QN);
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always @*
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if (~ENA) Q <= D;
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assign QN = ~Q;
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endmodule
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module dlatchsr(input ENA, D, CLEAR, PRESET, output reg Q, output QN);
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always @*
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if (CLEAR) Q <= 1'b0;
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else if (PRESET) Q <= 1'b1;
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else if (ENA) Q <= D;
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assign QN = ~Q;
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endmodule
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