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https://github.com/YosysHQ/yosys
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104 lines
2.5 KiB
Plaintext
104 lines
2.5 KiB
Plaintext
pattern xilinx_dsp
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state <SigBit> clock
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state <SigSpec> sigPused
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match dsp
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select dsp->type.in(\DSP48E1)
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endmatch
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match ffA
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select ffA->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffA, \CLK_POLARITY).as_bool()
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filter param(dsp, \AREG).as_int() == 0
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filter !port(dsp, \A).remove_const().empty()
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filter includes(port(ffA, \Q).to_sigbit_set(), port(dsp, \A).remove_const().to_sigbit_set())
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optional
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endmatch
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code clock
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if (ffA)
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clock = port(ffA, \CLK).as_bit();
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endcode
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match ffB
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select ffB->type.in($dff)
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// DSP48E1 does not support clock inversion
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select param(ffB, \CLK_POLARITY).as_bool()
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filter param(dsp, \BREG).as_int() == 0
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filter !port(dsp, \B).remove_const().empty()
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filter includes(port(ffB, \Q).to_sigbit_set(), port(dsp, \B).remove_const().to_sigbit_set())
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optional
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endmatch
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code clock
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if (ffB) {
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SigBit c = port(ffB, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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// Extract the bits of P that actually have a consumer
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// (as opposed to being a dummy)
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code sigPused
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SigSpec P = port(dsp, \P);
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for (int i = 0; i < GetSize(P); i++)
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if (P[i].wire && nusers(P[i]) > 1)
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sigPused.append(P[i]);
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endcode
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match ffP
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if !sigPused.empty()
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select ffP->type.in($dff)
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select nusers(port(ffP, \D)) == 2
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// DSP48E1 does not support clock inversion
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select param(ffP, \CLK_POLARITY).as_bool()
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filter param(dsp, \PREG).as_int() == 0
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filter param(ffP, \WIDTH).as_int() >= GetSize(sigPused)
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filter includes(port(ffP, \D).to_sigbit_set(), sigPused.to_sigbit_set())
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optional
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endmatch
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//// $mux cell left behind by dff2dffe
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//// would prefer not to run 'opt_expr -mux_undef'
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//// since that would lose information helpful for
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//// efficient wide-mux inference
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//match muxP
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// if !sigPused.empty() && !ffP
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// select muxP->type.in($mux)
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// select nusers(port(muxP, \B)) == 2
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// select port(muxP, \A).is_fully_undef()
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// filter param(muxP, \WIDTH).as_int() >= GetSize(sigPused)
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// filter includes(port(muxP, \B).to_sigbit_set(), sigPused.to_sigbit_set())
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// optional
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//endmatch
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//
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//match ffY
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// if muxP
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// select ffY->type.in($dff, $dffe)
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// select nusers(port(ffY, \D)) == 2
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// // DSP48E1 does not support clock inversion
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// select param(ffY, \CLK_POLARITY).as_bool()
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// filter param(ffY, \WIDTH).as_int() >= GetSize(sigPused)
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// filter includes(port(ffY, \D).to_sigbit_set(), port(muxP, \Y).to_sigbit_set())
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//endmatch
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code ffP clock
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// if (ffY)
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// ffP = ffY;
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if (ffP) {
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SigBit c = port(ffP, \CLK).as_bit();
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if (clock != SigBit() && c != clock)
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reject;
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clock = c;
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}
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endcode
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