yosys/tests/memories/nordports.ys at 9fa27dae3cc68205eab8d9d06302ace2bc6ddf41 - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-10-30 19:22:31 +00:00

Martin Povišer e82e5f8b13 rtlil: Adjust internal check for $mem_v2 cells

There's a mismatch between what `kernel/mem.cc` emits for memories
with no read ports and what the internal RTLIL check expects.

The point of dispute it whether some of the parameters relating to read
ports have a zero-width value in this case. The `mem.cc` code says no,
the internal checker says yes.

Surveying the other `$mem_v2` parameters, and internal cell parameters
in general, I am inclined to side with the `mem.cc` code.

This breaks RTLIL compatibility but for an obscure edge case.

2024-11-08 15:18:43 +01:00

9 lines

188 B

Text

Raw Blame History

 # check memory_collect doesn't produce invalid RTLIL on a memory w/o read ports
 read_rtlil <<EOF
 autoidx 1
 attribute \top 1
 module \top
   memory width 4 size 3 \foo
 end
 EOF
 memory_collect