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yosys/tests/verilog
Zachary Snow 73d611990d
Merge pull request #2578 from zachjs/genblk-port
verlog: allow shadowing module ports within generate blocks
2021-02-11 10:26:49 -05:00
..
.gitignore Update .gitignore 2020-10-01 15:53:14 +01:00
atom_type_signedness.ys Add missing is_signed to type_atom 2021-02-11 15:05:38 +01:00
block_labels.ys Add check of begin/end labels for genblock 2021-02-04 17:16:30 +01:00
bug656.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
bug656.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
bug2037.ys
bug2042-sv.ys
bug2042.ys
bug2493.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
const_arst.ys
const_sr.ys
genblk_case.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_case.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
genblk_port_decl.ys verlog: allow shadowing module ports within generate blocks 2021-02-07 11:48:39 -05:00
hidden_decl.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
run-test.sh
task_attr.ys
unnamed_block.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
unnamed_genblk.sv verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
unnamed_genblk.ys verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
upto.ys
wire_and_var.sv sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00
wire_and_var.ys sv: fix support wire and var data type modifiers 2021-01-20 09:16:21 -07:00