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63457de80e
Move the operand commute that puts the wider operand on A ahead of the min-width checks. Checking the min-widths first made an asymmetric rule (DSP_A_MINWIDTH != DSP_B_MINWIDTH) match only products that already had the wider operand on A; a product in the other order was rejected before the normalization.
32 lines
832 B
Text
32 lines
832 B
Text
# Test operand-order normalization: a 4x13 product with an asymmetric rule
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# (A_MIN=10, B_MIN=4) fails in this order (A=4 < A_MIN) but maps to one DSP
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# cell once the wide operand is normalized onto A.
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read_verilog <<EOF
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module top(a, b, y);
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input signed [3:0] a;
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input signed [12:0] b;
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output signed [16:0] y;
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assign y = a * b;
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endmodule
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EOF
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read_verilog -lib <<EOF
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module \$__MUL18X18 (A, B, Y);
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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input [A_WIDTH-1:0] A;
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input [B_WIDTH-1:0] B;
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output [Y_WIDTH-1:0] Y;
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endmodule
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EOF
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hierarchy -top top
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proc
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techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=10 -D DSP_B_MINWIDTH=4 -D DSP_NAME=\$__MUL18X18
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select -module top
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select -assert-count 1 t:\$__MUL18X18
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