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yosys/passes
whitequark 9f0892159e flatten, techmap: don't canonicalize tpl driven bits via sigmap.
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.
2020-08-26 16:29:42 +00:00
..
cmds Add new builtin FF types 2020-06-23 15:40:02 +02:00
equiv equiv_induct: Fix up assumption for $equiv cells in -undef mode. 2020-07-27 18:36:13 +02:00
fsm Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
hierarchy Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
memory memory_dff: Refactor to use FfInitVals. 2020-07-24 11:22:31 +02:00
opt Merge pull request #2344 from YosysHQ/mwk/opt_share-fixes 2020-08-20 16:24:53 +02:00
pmgen Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signed 2020-08-20 16:23:07 +02:00
proc proc: Add -nomux switch 2020-08-20 22:58:08 +02:00
sat async2sync: Support all FF types. 2020-07-30 20:22:03 +02:00
techmap flatten, techmap: don't canonicalize tpl driven bits via sigmap. 2020-08-26 16:29:42 +00:00
tests Ensure \A_SIGNED is never used with $shiftx 2020-08-18 19:36:24 +02:00