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Code Activity
yosys/techlibs/common
History
whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
2018-12-05 17:13:27 +00:00
..
.gitignore
adff2dff.v
cellhelp.py
cells.lib
dff2ff.v Add dff2ff.v techmap file 2017-05-31 11:45:58 +02:00
gate2lut.v gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
Makefile.inc gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00
pmux2mux.v
prep.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
simcells.v Fix typo. 2018-12-05 17:13:27 +00:00
simlib.v Add $allconst and $allseq cell types 2018-02-23 13:14:47 +01:00
synth.cc Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
techmap.v Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00