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16 lines
299 B
Plaintext
16 lines
299 B
Plaintext
read_verilog opt_lut.v
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synth_ice40
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ice40_unlut
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design -save preopt
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opt_lut
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design -stash postopt
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design -copy-from preopt -as preopt top
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design -copy-from postopt -as postopt top
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equiv_make preopt postopt equiv
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techmap -map ice40_carry.v
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prep -flatten -top equiv
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equiv_induct
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equiv_status -assert
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