Clifford Wolf da1c8d8d3d Merge pull request #772 from whitequark/synth_lut ... synth: add k-LUT mode		2019-01-02 15:44:57 +01:00
..
.gitignore
adff2dff.v
cellhelp.py
cells.lib
cmp2lut.v	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
dff2ff.v	Add dff2ff.v techmap file	2017-05-31 11:45:58 +02:00
gate2lut.v	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	2018-12-05 17:13:27 +00:00
Makefile.inc	cmp2lut: new techmap pass.	2019-01-02 07:53:31 +00:00
pmux2mux.v
prep.cc	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
simcells.v	Fix typo.	2018-12-05 17:13:27 +00:00
simlib.v	Add $allconst and $allseq cell types	2018-02-23 13:14:47 +01:00
synth.cc	Merge pull request #772 from whitequark/synth_lut	2019-01-02 15:44:57 +01:00
techmap.v