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yosys/techlibs/ice40
2019-04-21 21:40:11 +01:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments 2019-04-21 21:40:11 +01:00
ice40_braminit.cc
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
ice40_unlut.cc
latches_map.v
Makefile.inc
synth_ice40.cc