Sylvain Munaut acd9eeef7c ice40: Fix SPRAM model to keep data stable if chipselect is low ... According to the official simulation model, and also cross-checked on real hardware, the data output of the SPRAM when chipselect is low is kept stable. It doesn't go undefined. Signed-off-by: Sylvain Munaut <tnt@246tNt.com>		2020-03-14 21:01:42 +01:00
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tests	Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"	2019-08-12 12:06:45 -07:00
.gitignore	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
abc9_model.v	ice40: specify fixes	2020-02-27 10:17:29 -08:00
arith_map.v	ice40: reduce ABC9 internal fanout warnings with a param for CI->I3	2020-01-24 11:59:48 -08:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	ice40: use 2 bits for READ/WRITE MODE for SB_RAM map	2019-02-28 16:23:40 -08:00
cells_map.v	xilinx/ice40/ecp5: undo permuting LUT masks in lut_map	2020-01-27 13:30:27 -08:00
cells_sim.v	ice40: Fix SPRAM model to keep data stable if chipselect is low	2020-03-14 21:01:42 +01:00
dsp_map.v	Rework ice40_dsp to map to SB_MAC16 earlier, and check before packing	2019-08-08 12:56:05 -07:00
ice40_braminit.cc	substr() -> compare()	2019-08-07 12:20:08 -07:00
ice40_ffinit.cc	ice40: Demote conflicting FF init values to a warning	2019-12-31 02:38:10 +01:00
ice40_ffssr.cc	ice40: Honor the "dont_touch" attribute in FFSSR pass	2018-12-08 22:46:28 +01:00
ice40_opt.cc	Fix $lut input ordering -- SigSpec(std::initializer_list<>) is backwards	2020-01-27 14:02:13 -08:00
latches_map.v	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
Makefile.inc	ice40: move over to specify blocks for -abc9	2020-02-27 10:17:29 -08:00
synth_ice40.cc	Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc	2020-03-03 19:15:41 +01:00