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tests
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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.gitignore
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abc9_map.v
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Adding (* techmap_autopurge *) to FD* in abc9_map.v
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2020-01-14 12:22:21 -08:00 |
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abc9_model.v
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Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0
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2020-01-22 14:22:03 -08:00 |
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abc9_unmap.v
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2020-01-06 15:02:44 -08:00 |
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abc9_xc7.box
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Fix abc9_xc7.box comments
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2020-01-07 17:00:38 -08:00 |
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abc9_xc7.lut
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abc9_xc7_nowide.lut
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arith_map.v
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Deprecate `_CLB_CARRY from +/xilinx/arith_map.v since #1623
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2020-01-17 12:02:46 -08:00 |
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brams_init.py
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cells_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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cells_sim.v
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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cells_xtra.py
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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cells_xtra.v
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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lut_map.v
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xilinx/ice40/ecp5: undo permuting LUT masks in lut_map
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2020-01-27 13:30:27 -08:00 |
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lutrams.txt
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lutrams_map.v
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Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
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2019-12-16 12:06:47 -08:00 |
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Makefile.inc
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xilinx: Add xilinx_dffopt pass (#1557)
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2019-12-18 13:43:43 +01:00 |
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mux_map.v
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synth_xilinx.cc
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synth_xilinx: cleanup help
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2020-01-28 17:48:43 -08:00 |
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xc3s_mult_map.v
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xc3sda_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc4v_dsp_map.v
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xc5v_dsp_map.v
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xc6s_brams.txt
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xc6s_brams_map.v
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xc6s_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc6s_ff_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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xc7_brams_map.v
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xc7_dsp_map.v
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xc7_ff_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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xc7_xcu_brams.txt
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Add unconditional match blocks for force RAM
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2019-12-16 13:31:15 -08:00 |
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xcu_brams_map.v
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xcu_dsp_map.v
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xcup_urams.txt
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xcup_urams_map.v
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xilinx_dffopt.cc
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xilinx_dffopt: Keep order of LUT inputs.
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2019-12-19 18:01:43 +01:00 |
