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17 lines
340 B
Verilog
17 lines
340 B
Verilog
// expect-wr-ports 1
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// expect-rd-ports 1
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// expect-rd-clk \clk
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module top(input clk, input we, re, reset, input [7:0] addr, wdata, output reg [7:0] rdata);
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reg [7:0] bram[0:255];
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(* keep *) reg dummy;
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always @(posedge clk)
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if (reset)
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dummy <= 1'b0;
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else if (re)
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rdata <= bram[addr];
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else if (we)
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bram[addr] <= wdata;
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endmodule
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