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Code Activity
yosys/backends/cxxrtl
History
whitequark 9b39c6f744 cxxrtl: emit debug information for alias wires. 
Alias wires can represent a significant chunk of the design in highly
hierarchical designs; in Minerva SRAM, there are 273 member wires and
527 alias wires. Showing them in every hierarchy level significantly
improves usability.
2020-06-08 17:09:49 +00:00
..
cxxrtl.h cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
cxxrtl_backend.cc cxxrtl: emit debug information for alias wires. 2020-06-08 17:09:49 +00:00
cxxrtl_capi.cc cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
cxxrtl_capi.h cxxrtl: add a C API for driving and introspecting designs. 2020-06-06 21:12:55 +00:00
cxxrtl_vcd.h cxxrtl: only write VCD values that were actually updated. 2020-06-07 03:48:00 +00:00
cxxrtl_vcd_capi.cc cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
cxxrtl_vcd_capi.h cxxrtl: add a C API for writing VCD dumps. 2020-06-07 03:48:00 +00:00
Makefile.inc cxxrtl: rename cxxrtl.cc→cxxrtl_backend.cc. 2020-06-07 03:48:40 +00:00