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https://github.com/YosysHQ/yosys
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A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it.
65 lines
1.9 KiB
Makefile
65 lines
1.9 KiB
Makefile
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OBJS += passes/techmap/techmap.o
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OBJS += passes/techmap/simplemap.o
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OBJS += passes/techmap/dfflibmap.o
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OBJS += passes/techmap/maccmap.o
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OBJS += passes/techmap/libparse.o
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ifeq ($(ENABLE_ABC),1)
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OBJS += passes/techmap/abc.o
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OBJS += passes/techmap/abc9.o
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ifneq ($(ABCEXTERNAL),)
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passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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passes/techmap/abc9.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
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endif
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endif
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ifneq ($(SMALL),1)
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OBJS += passes/techmap/iopadmap.o
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OBJS += passes/techmap/clkbufmap.o
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OBJS += passes/techmap/hilomap.o
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OBJS += passes/techmap/extract.o
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OBJS += passes/techmap/extract_fa.o
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OBJS += passes/techmap/extract_counter.o
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OBJS += passes/techmap/extract_reduce.o
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OBJS += passes/techmap/alumacc.o
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OBJS += passes/techmap/dff2dffe.o
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OBJS += passes/techmap/dffinit.o
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OBJS += passes/techmap/pmuxtree.o
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OBJS += passes/techmap/muxcover.o
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OBJS += passes/techmap/aigmap.o
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OBJS += passes/techmap/tribuf.o
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OBJS += passes/techmap/lut2mux.o
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OBJS += passes/techmap/nlutmap.o
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OBJS += passes/techmap/dffsr2dff.o
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OBJS += passes/techmap/shregmap.o
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OBJS += passes/techmap/deminout.o
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OBJS += passes/techmap/insbuf.o
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OBJS += passes/techmap/attrmvcp.o
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OBJS += passes/techmap/attrmap.o
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OBJS += passes/techmap/zinit.o
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OBJS += passes/techmap/dff2dffs.o
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OBJS += passes/techmap/flowmap.o
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endif
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GENFILES += passes/techmap/techmap.inc
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passes/techmap/techmap.inc: techlibs/common/techmap.v
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$(Q) mkdir -p $(dir $@)
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$(P) echo "// autogenerated from $<" > $@.new
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$(Q) echo "static char stdcells_code[] = {" >> $@.new
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$(Q) od -v -td1 -An $< | $(SED) -e 's/[0-9][0-9]*/&,/g' >> $@.new
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$(Q) echo "0};" >> $@.new
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$(Q) mv $@.new $@
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passes/techmap/techmap.o: passes/techmap/techmap.inc
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ifneq ($(CONFIG),emcc)
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TARGETS += yosys-filterlib$(EXE)
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EXTRA_OBJS += passes/techmap/filterlib.o
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yosys-filterlib$(EXE): passes/techmap/filterlib.o
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$(Q) mkdir -p $(dir $@)
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$(P) $(LD) -o yosys-filterlib$(EXE) $(LDFLAGS) $^ $(LDLIBS)
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endif
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