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652a1b9806
The B port is for single-bit summands. These can just as well be represented as an additional summand on the A port (which supports summands of arbitrary width). An upcoming `$macc_v2` cell won't be special-casing single-bit summands in any way. In preparation, make the following changes: * remove the `bit_ports` field from the `Macc` helper (instead add any single-bit summands to `ports` next to other summands) * leave `B` empty on cells emitted from `Macc::to_cell`
50 lines
1.2 KiB
Text
50 lines
1.2 KiB
Text
# We don't set the B port on $macc cells anymore,
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# test compatibility with older RTLIL files which can
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# have the B port populated
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read_verilog <<EOF
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module gold(input signed [2:0] a1, input signed [2:0] b1,
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input [1:0] a2, input [3:0] b2, input c, input d, output signed [3:0] y);
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wire signed [3:0] ab1;
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assign ab1 = a1 * b1;
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assign y = ab1 + a2*b2 + c + d + 1;
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endmodule
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EOF
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prep
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# test the model for $macc including the retired B parameter
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# matches the gold module
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read_rtlil <<EOF
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attribute \src "<<EOF:1.1-4.10"
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module \gate
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wire width 3 input 1 signed \a1
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wire width 2 input 3 \a2
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wire width 3 input 2 signed \b1
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wire width 4 input 4 \b2
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wire input 5 \c
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wire input 6 \d
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wire width 4 output 7 signed \y
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cell $macc $1
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parameter \A_WIDTH 12
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parameter \B_WIDTH 3
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parameter \CONFIG 20'01010000011011010011
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parameter \CONFIG_WIDTH 20
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parameter \Y_WIDTH 4
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connect \A { \a2 \b2 \b1 \a1 }
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connect \B { \d \c 1'1 }
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connect \Y \y
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end
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end
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EOF
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design -save gold_gate
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equiv_make gold gate equiv
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equiv_induct equiv
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equiv_status -assert equiv
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design -load gold_gate
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maccmap gate
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equiv_make gold gate equiv
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equiv_induct equiv
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equiv_status -assert equiv
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