Marcelina Kościelnicka 347dd01c2f xilinx: Fix srl regression. ... Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.		2020-07-12 23:41:27 +02:00
..
.gitignore
abc9_dff.ys	abc9_ops: update messaging (credit to @Xiretza for spotting)	2020-05-30 08:57:48 -07:00
add_sub.ys	xilinx: Initial support for LUT4 devices.	2020-02-07 09:03:22 +01:00
adffs.ys
attributes_test.ys
blockram.ys
bug1460.ys
bug1462.ys
bug1480.ys	Cleanup tests	2020-02-27 10:17:29 -08:00
bug1598.ys
bug1605.ys
counter.ys
dffs.ys	abc9_ops: -reintegrate to use derived_type for box_ports	2020-02-05 14:46:48 -08:00
dsp_cascade.ys
dsp_fastfir.ys
dsp_simd.ys
fsm.ys	Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"	2020-02-27 10:17:29 -08:00
latches.ys
logic.ys
lutram.ys	xilinx: Add support for LUT RAM on LUT4-based devices.	2020-02-07 09:03:22 +01:00
macc.sh
macc.v	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc.ys	tests: xilinx macc test to have initval, shorten BMC depth for runtime	2020-05-25 10:09:05 -07:00
macc_tb.v
mul.ys
mul_unsigned.v
mul_unsigned.ys
mux.ys	Add force_downto and force_upto wire attributes.	2020-05-19 01:42:40 +02:00
mux_lut4.ys	xilinx: Initial support for LUT4 devices.	2020-02-07 09:03:22 +01:00
nosrl.ys	xilinx: Fix srl regression.	2020-07-12 23:41:27 +02:00
opt_lut_ins.ys
pmgen_xilinx_srl.ys	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
run-test.sh
shifter.ys
tribuf.sh	fix argument order for macOS compatibility	2020-03-18 15:11:49 +01:00
tribuf.ys
xilinx_dffopt.ys	xilinx: xilinx_dffopt to read cells_sim.v; fix test	2020-04-22 16:25:23 -07:00
xilinx_dffopt_blacklist.txt
xilinx_dsp.ys	tests: read +/xilinx/cell_sim.v before xilinx_dsp test	2020-04-22 17:50:30 -07:00
xilinx_srl.v	tests: fix some test warnings	2020-05-25 10:07:58 -07:00
xilinx_srl.ys