yosys/tests/opt/opt_ff_sat.v at 9a468f81c412f8b63d25e739f28932815c6882fb - mirrors/yosys - Libre-Chip.org

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Bogdan Vukobratovic 9a468f81c4 Optimizing DFFs whose initial value prevents their value from changing

This is a proof of concept implementation that invokes SAT solver via Pass::call
method.

2019-05-28 08:48:21 +02:00

16 lines

219 B

Verilog

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 module top(
 					 input 	clk,
 					 input 	a,
 					 output b
 					 );
   reg 						b_reg;
   initial begin
     b_reg <= 0;
   end
   assign b = b_reg;
   always @(posedge clk) begin
     b_reg <= a && b_reg;
   end
 endmodule