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yosys/techlibs/common
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Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve 
abc9: -dff improvements
2020-06-04 08:15:25 -07:00
..
.gitignore
abc9_map.v abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_ 2020-05-14 16:44:35 -07:00
abc9_model.v
abc9_unmap.v abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
adff2dff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cellhelp.py
cells.lib
cmp2lcu.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cmp2lut.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
dff2ff.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
pmux2mux.v
prep.cc
simcells.v
simlib.v Add flooring division operator 2020-05-28 22:59:04 +02:00
synth.cc
techmap.v Add flooring division operator 2020-05-28 22:59:04 +02:00