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21 lines
450 B
Systemverilog
21 lines
450 B
Systemverilog
module producer(
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output logic [3:0] out
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);
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assign out = 4'hA;
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endmodule
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module top(
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output logic [3:0] out0, out1, out2, out3
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);
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logic [3:0] v[1:0];
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logic [1:0] u[1:0];
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logic [1:0] t[1:0];
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producer p0(v[0]);
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producer p1({v[1]});
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producer p2({u[1], u[0]});
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producer p3({{t[1]}, {t[0]}});
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assign out0 = v[0];
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assign out1 = v[1];
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assign out2 = {u[1], u[0]};
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assign out3 = {t[1], t[0]};
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endmodule
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