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42 lines
1.4 KiB
Verilog
42 lines
1.4 KiB
Verilog
(* techmap_celltype = "$__REGFILE_[AS][AS]_" *)
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module \$__REGFILE_XX_ (...);
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parameter _TECHMAP_CELLTYPE_ = "";
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localparam [0:0] B_SYNC = _TECHMAP_CELLTYPE_[15:8] == "S";
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localparam [0:0] A_SYNC = _TECHMAP_CELLTYPE_[23:16] == "S";
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localparam WIDTH = 4;
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localparam ABITS = 5;
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input [WIDTH-1:0] PORT_W_WR_DATA;
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input [ABITS-1:0] PORT_W_ADDR;
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input PORT_W_WR_EN;
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output [WIDTH-1:0] PORT_A_RD_DATA;
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input [ABITS-1:0] PORT_A_ADDR;
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output [WIDTH-1:0] PORT_B_RD_DATA;
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input [ABITS-1:0] PORT_B_ADDR;
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// Unused - we have a shared clock - but keep techmap happy
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input PORT_W_CLK;
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input PORT_A_CLK;
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input PORT_B_CLK;
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input CLK_CLK;
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RegFile_32x4 #(
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.AD_reg(A_SYNC),
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.BD_reg(B_SYNC)
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) _TECHMAP_REPLACE_ (
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.D0(PORT_W_WR_DATA[0]), .D1(PORT_W_WR_DATA[1]), .D2(PORT_W_WR_DATA[2]), .D3(PORT_W_WR_DATA[3]),
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.W_ADR0(PORT_W_ADDR[0]), .W_ADR1(PORT_W_ADDR[1]), .W_ADR2(PORT_W_ADDR[2]), .W_ADR3(PORT_W_ADDR[3]), .W_ADR4(PORT_W_ADDR[4]),
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.W_en(PORT_W_WR_EN),
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.AD0(PORT_A_RD_DATA[0]), .AD1(PORT_A_RD_DATA[1]), .AD2(PORT_A_RD_DATA[2]), .AD3(PORT_A_RD_DATA[3]),
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.A_ADR0(PORT_A_ADDR[0]), .A_ADR1(PORT_A_ADDR[1]), .A_ADR2(PORT_A_ADDR[2]), .A_ADR3(PORT_A_ADDR[3]), .A_ADR4(PORT_A_ADDR[4]),
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.BD0(PORT_B_RD_DATA[0]), .BD1(PORT_B_RD_DATA[1]), .BD2(PORT_B_RD_DATA[2]), .BD3(PORT_B_RD_DATA[3]),
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.B_ADR0(PORT_B_ADDR[0]), .B_ADR1(PORT_B_ADDR[1]), .B_ADR2(PORT_B_ADDR[2]), .B_ADR3(PORT_B_ADDR[3]), .B_ADR4(PORT_B_ADDR[4]),
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.CLK(CLK_CLK)
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);
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endmodule
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