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https://github.com/YosysHQ/yosys
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149 lines
3.5 KiB
Verilog
149 lines
3.5 KiB
Verilog
module $__EFINIX_5K_ (...);
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parameter INIT = 0;
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parameter OPTION_WRITE_MODE = "READ_FIRST";
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parameter PORT_R_WIDTH = 20;
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parameter PORT_R_CLK_POL = 1;
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parameter PORT_W_WIDTH = 20;
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parameter PORT_W_CLK_POL = 1;
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input PORT_R_CLK;
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input PORT_R_RD_EN;
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input [11:0] PORT_R_ADDR;
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output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
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input PORT_W_CLK;
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input PORT_W_WR_EN;
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input [11:0] PORT_W_ADDR;
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input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
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localparam IS_5BIT = PORT_R_WIDTH >= 5 && PORT_W_WIDTH >= 5;
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localparam RADDR_WIDTH =
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PORT_R_WIDTH == 1 ? 12 :
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PORT_R_WIDTH == 2 ? 11 :
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PORT_R_WIDTH == 5 ? 10 :
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PORT_R_WIDTH == 10 ? 9 :
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8;
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localparam WADDR_WIDTH =
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PORT_W_WIDTH == 1 ? 12 :
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PORT_W_WIDTH == 2 ? 11 :
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PORT_W_WIDTH == 5 ? 10 :
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PORT_W_WIDTH == 10 ? 9 :
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8;
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localparam READ_WIDTH =
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PORT_R_WIDTH == 1 ? 1 :
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PORT_R_WIDTH == 2 ? 2 :
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PORT_R_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
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PORT_R_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
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(IS_5BIT ? 20 : 16);
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localparam WRITE_WIDTH =
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PORT_W_WIDTH == 1 ? 1 :
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PORT_W_WIDTH == 2 ? 2 :
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PORT_W_WIDTH == 5 ? (IS_5BIT ? 5 : 4) :
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PORT_W_WIDTH == 10 ? (IS_5BIT ? 10 : 8) :
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(IS_5BIT ? 20 : 16);
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wire [RADDR_WIDTH-1:0] RADDR = PORT_R_ADDR[11:12-RADDR_WIDTH];
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wire [WADDR_WIDTH-1:0] WADDR = PORT_W_ADDR[11:12-WADDR_WIDTH];
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wire [WRITE_WIDTH-1:0] WDATA;
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wire [READ_WIDTH-1:0] RDATA;
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generate
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case (WRITE_WIDTH)
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1: assign WDATA = PORT_W_WR_DATA;
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2: assign WDATA = PORT_W_WR_DATA;
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4: assign WDATA = PORT_W_WR_DATA[3:0];
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5: assign WDATA = PORT_W_WR_DATA;
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8: assign WDATA = {
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PORT_W_WR_DATA[8:5],
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PORT_W_WR_DATA[3:0]
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};
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10: assign WDATA = PORT_W_WR_DATA;
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16: assign WDATA = {
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PORT_W_WR_DATA[18:15],
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PORT_W_WR_DATA[13:10],
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PORT_W_WR_DATA[8:5],
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PORT_W_WR_DATA[3:0]
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};
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20: assign WDATA = PORT_W_WR_DATA;
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endcase
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case (READ_WIDTH)
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1: assign PORT_R_RD_DATA = RDATA;
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2: assign PORT_R_RD_DATA = RDATA;
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4: assign PORT_R_RD_DATA[3:0] = RDATA;
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5: assign PORT_R_RD_DATA = RDATA;
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8: assign {
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PORT_R_RD_DATA[8:5],
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PORT_R_RD_DATA[3:0]
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} = RDATA;
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10: assign PORT_R_RD_DATA = RDATA;
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16: assign {
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PORT_R_RD_DATA[18:15],
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PORT_R_RD_DATA[13:10],
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PORT_R_RD_DATA[8:5],
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PORT_R_RD_DATA[3:0]
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} = RDATA;
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20: assign PORT_R_RD_DATA = RDATA;
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endcase
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endgenerate
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function [255:0] init_slice;
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input integer idx;
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integer i;
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if (IS_5BIT)
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init_slice = INIT[idx * 256 +: 256];
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else if (idx > 16)
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init_slice = 0;
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else
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for (i = 0; i < 64; i = i + 1)
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init_slice[i*4+:4] = INIT[(idx * 64 + i) * 5+:4];
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endfunction
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EFX_RAM_5K #(
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.READ_WIDTH(READ_WIDTH),
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.WRITE_WIDTH(WRITE_WIDTH),
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.OUTPUT_REG(1'b0),
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.RCLK_POLARITY(PORT_R_CLK_POL),
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.RE_POLARITY(1'b1),
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.WCLK_POLARITY(PORT_W_CLK_POL),
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.WE_POLARITY(1'b1),
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.WCLKE_POLARITY(1'b1),
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.WRITE_MODE(OPTION_WRITE_MODE),
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.INIT_0(init_slice('h00)),
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.INIT_1(init_slice('h01)),
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.INIT_2(init_slice('h02)),
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.INIT_3(init_slice('h03)),
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.INIT_4(init_slice('h04)),
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.INIT_5(init_slice('h05)),
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.INIT_6(init_slice('h06)),
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.INIT_7(init_slice('h07)),
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.INIT_8(init_slice('h08)),
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.INIT_9(init_slice('h09)),
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.INIT_A(init_slice('h0a)),
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.INIT_B(init_slice('h0b)),
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.INIT_C(init_slice('h0c)),
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.INIT_D(init_slice('h0d)),
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.INIT_E(init_slice('h0e)),
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.INIT_F(init_slice('h0f)),
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.INIT_10(init_slice('h10)),
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.INIT_11(init_slice('h11)),
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.INIT_12(init_slice('h12)),
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.INIT_13(init_slice('h13)),
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) _TECHMAP_REPLACE_ (
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.WDATA(WDATA),
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.WADDR(WADDR),
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.WE(PORT_W_WR_EN),
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.WCLK(PORT_W_CLK),
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.WCLKE(1'b1),
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.RDATA(RDATA),
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.RADDR(RADDR),
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.RE(PORT_R_RD_EN),
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.RCLK(PORT_R_CLK)
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);
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endmodule
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