mirror of
https://github.com/YosysHQ/yosys
synced 2026-01-20 17:14:44 +00:00
872 lines
14 KiB
Text
872 lines
14 KiB
Text
###################################################################
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# Reduce AND Test Cases
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###################################################################
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log -header "Simple positive reduce AND case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = &a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 7 t:$and
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design -reset
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log -pop
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log -header "Two reduce ANDs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (&a) | (&b);
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 14 t:$and
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design -reset
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log -pop
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log -header "Reduce AND on bit slice"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = &a[3:0];
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$and
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design -reset
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log -pop
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log -header "Single bit input"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire x
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);
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assign x = &a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 0 t:$and
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design -reset
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log -pop
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log -header "Unbalanced"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x
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);
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assign x = &a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$and
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design -reset
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log -pop
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###################################################################
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# Reduce OR Test Cases
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###################################################################
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log -header "Simple positive reduce OR case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = |a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 7 t:$or
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design -reset
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log -pop
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log -header "Two reduce ORs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (|a) & (|b);
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 14 t:$or
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design -reset
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log -pop
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log -header "Reduce OR on bit slice"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = |a[3:0];
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$or
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design -reset
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log -pop
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log -header "Single bit input"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire x
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);
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assign x = |a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 0 t:$or
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design -reset
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log -pop
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log -header "Unbalanced"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x
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);
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assign x = |a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$or
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design -reset
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log -pop
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###################################################################
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# Reduce XOR Test Cases
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###################################################################
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log -header "Simple positive reduce XOR case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = ^a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 7 t:$xor
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design -reset
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log -pop
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log -header "Two reduce XORs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (^a) & (^b);
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 14 t:$xor
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design -reset
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log -pop
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log -header "Reduce XOR on bit slice"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = ^a[3:0];
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 3 t:$xor
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design -reset
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log -pop
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log -header "Single bit input"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire x
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);
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assign x = ^a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 0 t:$xor
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design -reset
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log -pop
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log -header "Unbalanced"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x
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);
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assign x = ^a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 4 t:$xor
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design -reset
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log -pop
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###################################################################
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# Reduce XNOR Test Cases
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###################################################################
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log -header "Simple positive reduce XNOR case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = ~^a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-count 7 t:$xor
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design -reset
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log -pop
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log -header "Two reduce XNORs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (~^a) & (~^b);
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 2 t:$not
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select -assert-count 14 t:$xor
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design -reset
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log -pop
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log -header "Reduce XNOR on bit slice"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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output wire x
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);
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assign x = ~^a[3:0];
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-count 3 t:$xor
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design -reset
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log -pop
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log -header "Single bit input"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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output wire x
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);
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assign x = ~^a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 0 t:$xor
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design -reset
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log -pop
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log -header "Unbalanced"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [4:0] a,
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output wire x
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);
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assign x = ~^a;
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-count 4 t:$xor
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design -reset
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log -pop
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###################################################################
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# Break EQ Test Cases
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###################################################################
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log -header "Simple positive EQ case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (a == b);
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-count 7 t:$or
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select -assert-count 1 t:$xor
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design -reset
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log -pop
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log -header "EQ case with odd bit width and bit slice"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (a[4:0] == b[4:0]);
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endmodule
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EOF
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check -assert
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 1 t:$not
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select -assert-count 4 t:$or
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select -assert-count 1 t:$xor
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design -reset
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log -pop
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###################################################################
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# Break NE Test Cases
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###################################################################
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log -header "Simple positive NE case"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (a != b);
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endmodule
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EOF
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check -assert
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|
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# Check equivalence after breakreduce
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equiv_opt -assert breakreduce
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# Check final design has correct number of gates
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design -load postopt
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select -assert-count 0 t:$not
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select -assert-count 7 t:$or
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select -assert-count 1 t:$xor
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design -reset
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log -pop
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log -header "NE case with odd bit width and bit slice"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (a[4:0] != b[4:0]);
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endmodule
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EOF
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check -assert
|
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|
|
# Check equivalence after breakreduce
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|
equiv_opt -assert breakreduce
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|
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# Check final design has correct number of gates
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|
design -load postopt
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select -assert-count 0 t:$not
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select -assert-count 4 t:$or
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select -assert-count 1 t:$xor
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design -reset
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log -pop
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|
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###################################################################
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# Break Logic AND Test Cases
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###################################################################
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|
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log -header "Simple positive AND case"
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log -push
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design -reset
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|
read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [7:0] b,
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output wire x
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);
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assign x = (a && b);
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endmodule
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EOF
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|
check -assert
|
|
|
|
# Check equivalence after breakreduce
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|
equiv_opt -assert breakreduce
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|
# Check final design has correct number of gates
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|
design -load postopt
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select -assert-count 1 t:$and
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select -assert-count 14 t:$or
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|
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design -reset
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log -pop
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|
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log -header "Bit width mismatch and bit slicing"
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log -push
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design -reset
|
|
read_verilog <<EOF
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module top (
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input wire [5:0] a,
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input wire [4:0] b,
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output wire x
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);
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assign x = (a[3:0] && b);
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endmodule
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|
EOF
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|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 1 t:$and
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select -assert-count 7 t:$or
|
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|
|
design -reset
|
|
log -pop
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|
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|
log -header "Use bitwise AND and ensure it is not getting converted"
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|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
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|
input wire [7:0] a,
|
|
input wire [7:0] b,
|
|
output wire x
|
|
);
|
|
assign x = (a & b);
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 1 t:$and
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
###################################################################
|
|
# Break Logic OR Test Cases
|
|
###################################################################
|
|
|
|
log -header "Simple positive OR case"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a,
|
|
input wire [7:0] b,
|
|
output wire x
|
|
);
|
|
assign x = (a || b);
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 15 t:$or
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Bit width mismatch and bit slicing"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [5:0] a,
|
|
input wire [4:0] b,
|
|
output wire x
|
|
);
|
|
assign x = (a[3:0] || b);
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 8 t:$or
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Use bitwise OR and ensure it is not getting converted"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a,
|
|
input wire [7:0] b,
|
|
output wire x
|
|
);
|
|
assign x = (a | b);
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 1 t:$or
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
###################################################################
|
|
# Break Logic NOT Test Cases
|
|
###################################################################
|
|
|
|
log -header "Simple positive NOT case"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a,
|
|
output wire x
|
|
);
|
|
assign x = !a;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 1 t:$not
|
|
select -assert-count 7 t:$or
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Odd bit width"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [4:0] a,
|
|
output wire x
|
|
);
|
|
assign x = !a;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 1 t:$not
|
|
select -assert-count 4 t:$or
|
|
|
|
design -reset
|
|
log -pop
|
|
|
|
|
|
|
|
log -header "Use bitwise not and ensure it is not getting converted"
|
|
log -push
|
|
design -reset
|
|
read_verilog <<EOF
|
|
module top (
|
|
input wire [7:0] a,
|
|
output wire x
|
|
);
|
|
assign x = ~a;
|
|
endmodule
|
|
EOF
|
|
check -assert
|
|
|
|
# Check equivalence after breakreduce
|
|
equiv_opt -assert breakreduce
|
|
|
|
# Check final design has correct number of gates
|
|
design -load postopt
|
|
select -assert-count 0 t:$or
|
|
|
|
design -reset
|
|
log -pop
|