mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-11 11:43:38 +00:00
702ce405c1
This test is failing due to one of the changes present in this patchset. Adjust the test to match the newly-observed values. https://github.com/xobs/yosys/compare/smtbmc-msvc2-build-fixes...YosysHQ:xobs/pr1362 Signed-off-by: Sean Cross <sean@xobs.io>
10 lines
404 B
Plaintext
10 lines
404 B
Plaintext
read_verilog div_mod.v
|
|
hierarchy -top top
|
|
flatten
|
|
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
|
|
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
|
|
cd top # Constrain all select calls below inside the top module
|
|
select -assert-count 59 t:SB_LUT4
|
|
select -assert-count 41 t:SB_CARRY
|
|
select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D
|