mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-06 09:34:09 +00:00
13 lines
145 B
Plaintext
13 lines
145 B
Plaintext
ram distributed $__TRELLIS_DPR16X4_ {
|
|
abits 4;
|
|
width 4;
|
|
cost 4;
|
|
init any;
|
|
prune_rom;
|
|
port sw "W" {
|
|
clock anyedge;
|
|
}
|
|
port ar "R" {
|
|
}
|
|
}
|