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11 lines
181 B
Verilog
11 lines
181 B
Verilog
module uut_param_attr (I, O);
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(* PARAMETER_ATTRIBUTE = "attribute_content" *)
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parameter WIDTH = 1;
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input wire [WIDTH-1:0] I;
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output wire [WIDTH-1:0] O;
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assign O = I;
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endmodule
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