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30 lines
506 B
Verilog
30 lines
506 B
Verilog
module uut_forgen02(a, b, cin, y, cout);
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parameter WIDTH = 8;
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input [WIDTH-1:0] a, b;
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input cin;
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output [WIDTH-1:0] y;
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output cout;
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genvar i;
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wire [WIDTH-1:0] carry;
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generate
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for (i = 0; i < WIDTH; i=i+1) begin:adder
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wire [2:0] D;
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assign D[1:0] = { a[i], b[i] };
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if (i == 0) begin:chain
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assign D[2] = cin;
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end else begin:chain
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assign D[2] = carry[i-1];
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end
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assign y[i] = ^D;
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assign carry[i] = &D[1:0] | (^D[1:0] & D[2]);
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end
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endgenerate
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assign cout = carry[WIDTH-1];
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endmodule
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