3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-10-10 01:41:59 +00:00
yosys/techlibs/gowin
2025-10-08 07:47:22 +03:00
..
arith_map.v gowin: Fix X output of $alu techmap 2023-05-01 17:56:41 +02:00
brams.txt gowin: Change BYTE ENABLE handling. 2024-01-27 17:19:49 +10:00
brams_map.v gowin: Fix SDP write enable port. 2024-01-30 17:06:59 +10:00
cells_map.v gowin: add mux techmap and whitebox 2023-10-12 20:24:12 +08:00
cells_sim.v Merge aa86e6355e into 47ca09a016 2025-10-08 07:47:22 +03:00
cells_xtra.py Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw1n.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw2a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
cells_xtra_gw5a.v Gowin. Renaming inputs of the DCS primitive. 2025-09-20 16:22:23 +01:00
lutrams.txt gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
lutrams_map.v gowin: Use memory_libmap pass. 2022-05-18 17:32:56 +02:00
Makefile.inc gowin: split cells_xtra by family 2024-11-26 15:42:22 +01:00
synth_gowin.cc Remove .c_str() from stringf parameters 2025-09-01 23:34:42 +00:00