mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
38a24ec5cc
Co-authored-by: Claire Xenia Wolf <claire@clairexen.net> Signed-off-by: gatecat <gatecat@ds0.me>
4 lines
180 B
Verilog
4 lines
180 B
Verilog
// Any inverters not folded into LUTs are mapped to a LUT of their own
|
|
module \$__CC_NOT (input A, output Y);
|
|
CC_LUT1 #(.INIT(2'b01)) _TECHMAP_REPLACE_ (.I0(A), .O(Y));
|
|
endmodule
|