mirror of
https://github.com/YosysHQ/yosys
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79 lines
2.3 KiB
Verilog
79 lines
2.3 KiB
Verilog
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// > c60k28 (Viacheslav, VT) [at] yandex [dot] com
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// > Achronix eFPGA technology sim models. User must first simulate the generated \
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// > netlist before going to test it on board/custom chip.
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// > Changelog: 1) Removed unused VCC/GND modules
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// > 2) Altera comments here (?). Removed.
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// > 3) Reusing LUT sim model, removed wrong wires and parameters.
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module PADIN (output padout, input padin);
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assign padout = padin;
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endmodule
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module PADOUT (output padout, input padin, input oe);
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assign padout = padin;
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assign oe = oe;
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endmodule
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module LUT4 (output dout,
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input din0, din1, din2, din3);
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parameter [15:0] lut_function = 16'hFFFF;
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reg combout_rt;
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wire dataa_w;
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wire datab_w;
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wire datac_w;
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wire datad_w;
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assign dataa_w = din0;
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assign datab_w = din1;
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assign datac_w = din2;
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assign datad_w = din3;
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function lut_data;
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input [15:0] mask;
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input dataa, datab, datac, datad;
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reg [7:0] s3;
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reg [3:0] s2;
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reg [1:0] s1;
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begin
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s3 = datad ? mask[15:8] : mask[7:0];
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s2 = datac ? s3[7:4] : s3[3:0];
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s1 = datab ? s2[3:2] : s2[1:0];
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lut_data = dataa ? s1[1] : s1[0];
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end
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endfunction
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always @(dataa_w or datab_w or datac_w or datad_w) begin
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combout_rt = lut_data(lut_function, dataa_w, datab_w,
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datac_w, datad_w);
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end
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assign dout = combout_rt & 1'b1;
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endmodule
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module DFF (output reg q,
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input d, ck);
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always @(posedge ck)
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q <= d;
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endmodule
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