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Code Activity
yosys/passes/proc
History
Clifford Wolf 8b508dc90b Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst
2014-02-21 23:34:45 +01:00
..
Makefile.inc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc.cc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc_arst.cc Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
proc_clean.cc Added handling of multiple async paths in proc_arst 2013-10-19 00:50:13 +02:00
proc_dff.cc Added support for complex set-reset flip-flops in proc_dff 2013-10-24 16:54:05 +02:00
proc_init.cc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc_mux.cc Tiny cleanup in proc_mux.cc 2014-01-03 16:54:59 +01:00
proc_rmdead.cc Added help messages to proc_* passes 2013-03-01 09:26:29 +01:00