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tests
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xilinx: Add simulation model for DSP48 (Virtex 4).
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2020-01-29 01:40:00 +01:00 |
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.gitignore
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Added support for initialized xilinx brams
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2015-04-06 17:07:10 +02:00 |
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abc9_map.v
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xilinx: consider DSP48E1.ADREG
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2020-03-04 12:04:02 -08:00 |
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abc9_model.v
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xilinx: consider DSP48E1.ADREG
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2020-03-04 12:04:02 -08:00 |
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abc9_unmap.v
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xilinx: consider DSP48E1.ADREG
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2020-03-04 12:04:02 -08:00 |
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arith_map.v
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xilinx: Initial support for LUT4 devices.
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2020-02-07 09:03:22 +01:00 |
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brams_init.py
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synth_xilinx: Initial Spartan 6 block RAM inference support.
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2019-07-11 14:45:48 +02:00 |
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cells_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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cells_sim.v
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xilinx: consider DSP48E1.ADREG
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2020-03-04 12:04:02 -08:00 |
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cells_xtra.py
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Remove RAMB{18,36}E1 from cells_xtra.py
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2020-02-27 10:33:04 -08:00 |
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cells_xtra.v
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Get rid of (* abc9_{arrival,required} *) entirely
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2020-02-27 10:17:29 -08:00 |
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lut4_lutrams.txt
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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lut6_lutrams.txt
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xilinx: Add support for LUT RAM on LUT4-based devices.
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2020-02-07 09:03:22 +01:00 |
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lut_map.v
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xilinx: Initial support for LUT4 devices.
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2020-02-07 09:03:22 +01:00 |
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lutrams_map.v
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Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
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2019-12-16 12:06:47 -08:00 |
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Makefile.inc
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Auto-generate .box/.lut files from specify blocks
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2020-02-27 10:17:29 -08:00 |
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mux_map.v
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Change synth_xilinx's -nomux to -minmuxf <int>
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2019-06-24 10:04:01 -07:00 |
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synth_xilinx.cc
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Update xilinx for ABC9
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2020-02-27 10:17:29 -08:00 |
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xc2v_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc2v_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3s_mult_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc3sa_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3sda_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc3sda_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc4v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc5v_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc6s_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc6s_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc6s_dsp_map.v
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xilinx_dsp: Initial DSP48A/DSP48A1 support.
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2019-12-22 20:51:14 +01:00 |
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xc6s_ff_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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xc7_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xc7_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xc7_ff_map.v
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xilinx: Improve flip-flop handling.
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2019-12-18 13:43:43 +01:00 |
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xc7_xcu_brams.txt
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xcu_brams_map.v
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xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
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2020-02-07 01:00:29 +01:00 |
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xcu_dsp_map.v
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xilinx: Support multiplier mapping for all families.
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2019-10-22 18:06:57 +02:00 |
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xcup_urams.txt
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xilinx: Add URAM288 mapping for xcup
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2019-10-23 11:47:44 +01:00 |
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xcup_urams_map.v
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xilinx: Add URAM288 mapping for xcup
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2019-10-23 11:47:44 +01:00 |
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xilinx_dffopt.cc
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xilinx_dffopt: Keep order of LUT inputs.
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2019-12-19 18:01:43 +01:00 |
