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27 lines
569 B
Verilog
27 lines
569 B
Verilog
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(* top *)
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module hierarchy_top(a, b, y1, y2, y3, y4);
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input [3:0] a;
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input signed [3:0] b;
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output [7:0] y1, y2, y3, y4;
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// this version triggers a bug in Icarus Verilog
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// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
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// this version is handled correctly by Icarus Verilog
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submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
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endmodule
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(* gentb_skip *)
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module submod(a, b, y1, y2, y3, y4);
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parameter c = 0;
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parameter [7:0] d = 0;
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input [3:0] a, b;
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output [7:0] y1, y2, y3, y4;
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assign y1 = a;
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assign y2 = b;
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assign y3 = c;
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assign y4 = d;
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endmodule
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