mirror of
https://github.com/YosysHQ/yosys
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265 lines
7.2 KiB
Verilog
265 lines
7.2 KiB
Verilog
// Copyright 2020-2022 F4PGA Authors
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//
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// SPDX-License-Identifier: Apache-2.0
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module dsp_t1_20x18x64_cfg_ports (
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input [19:0] a_i,
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input [17:0] b_i,
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input [ 5:0] acc_fir_i,
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output [37:0] z_o,
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output [17:0] dly_b_o,
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input clock_i,
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input reset_i,
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input [2:0] feedback_i,
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input load_acc_i,
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input unsigned_a_i,
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input unsigned_b_i,
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input [2:0] output_select_i,
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input saturate_enable_i,
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input [5:0] shift_right_i,
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input round_i,
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input subtract_i,
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input register_inputs_i
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);
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parameter [19:0] COEFF_0 = 20'd0;
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parameter [19:0] COEFF_1 = 20'd0;
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parameter [19:0] COEFF_2 = 20'd0;
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parameter [19:0] COEFF_3 = 20'd0;
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QL_DSP2 # (
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.MODE_BITS ({COEFF_3, COEFF_2, COEFF_1, COEFF_0})
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) _TECHMAP_REPLACE_ (
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.a (a_i),
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.b (b_i),
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.acc_fir (acc_fir_i),
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.z (z_o),
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.dly_b (dly_b_o),
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.clk (clock_i),
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.reset (reset_i),
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.feedback (feedback_i),
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.load_acc (load_acc_i),
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.unsigned_a (unsigned_a_i),
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.unsigned_b (unsigned_b_i),
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.f_mode (1'b0), // No fracturation
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.output_select (output_select_i),
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.saturate_enable (saturate_enable_i),
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.shift_right (shift_right_i),
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.round (round_i),
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.subtract (subtract_i),
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.register_inputs (register_inputs_i)
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);
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endmodule
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module dsp_t1_10x9x32_cfg_ports (
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input [ 9:0] a_i,
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input [ 8:0] b_i,
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input [ 5:0] acc_fir_i,
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output [18:0] z_o,
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output [ 8:0] dly_b_o,
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(* clkbuf_sink *)
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input clock_i,
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input reset_i,
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input [2:0] feedback_i,
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input load_acc_i,
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input unsigned_a_i,
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input unsigned_b_i,
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input [2:0] output_select_i,
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input saturate_enable_i,
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input [5:0] shift_right_i,
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input round_i,
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input subtract_i,
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input register_inputs_i
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);
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parameter [9:0] COEFF_0 = 10'd0;
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parameter [9:0] COEFF_1 = 10'd0;
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parameter [9:0] COEFF_2 = 10'd0;
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parameter [9:0] COEFF_3 = 10'd0;
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wire [37:0] z;
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wire [17:0] dly_b;
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QL_DSP2 # (
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.MODE_BITS ({10'd0, COEFF_3,
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10'd0, COEFF_2,
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10'd0, COEFF_1,
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10'd0, COEFF_0})
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) _TECHMAP_REPLACE_ (
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.a ({10'd0, a_i}),
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.b ({ 9'd0, b_i}),
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.acc_fir (acc_fir_i),
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.z (z),
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.dly_b (dly_b),
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.clk (clock_i),
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.reset (reset_i),
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.feedback (feedback_i),
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.load_acc (load_acc_i),
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.unsigned_a (unsigned_a_i),
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.unsigned_b (unsigned_b_i),
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.f_mode (1'b1), // Enable fractuation, Use the lower half
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.output_select (output_select_i),
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.saturate_enable (saturate_enable_i),
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.shift_right (shift_right_i),
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.round (round_i),
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.subtract (subtract_i),
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.register_inputs (register_inputs_i)
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);
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assign z_o = z[18:0];
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assign dly_b_o = dly_b_o[8:0];
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endmodule
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module dsp_t1_20x18x64_cfg_params (
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input [19:0] a_i,
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input [17:0] b_i,
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input [ 5:0] acc_fir_i,
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output [37:0] z_o,
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output [17:0] dly_b_o,
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input clock_i,
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input reset_i,
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input [2:0] feedback_i,
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input load_acc_i,
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input unsigned_a_i,
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input unsigned_b_i,
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input subtract_i
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);
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parameter [19:0] COEFF_0 = 20'd0;
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parameter [19:0] COEFF_1 = 20'd0;
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parameter [19:0] COEFF_2 = 20'd0;
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parameter [19:0] COEFF_3 = 20'd0;
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parameter [2:0] OUTPUT_SELECT = 3'd0;
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parameter [0:0] SATURATE_ENABLE = 1'd0;
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parameter [5:0] SHIFT_RIGHT = 6'd0;
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parameter [0:0] ROUND = 1'd0;
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parameter [0:0] REGISTER_INPUTS = 1'd0;
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QL_DSP3 # (
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.MODE_BITS ({
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REGISTER_INPUTS,
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ROUND,
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SHIFT_RIGHT,
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SATURATE_ENABLE,
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OUTPUT_SELECT,
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1'b0, // Not fractured
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COEFF_3,
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COEFF_2,
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COEFF_1,
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COEFF_0
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})
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) _TECHMAP_REPLACE_ (
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.a (a_i),
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.b (b_i),
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.acc_fir (acc_fir_i),
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.z (z_o),
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.dly_b (dly_b_o),
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.clk (clock_i),
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.reset (reset_i),
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.feedback (feedback_i),
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.load_acc (load_acc_i),
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.unsigned_a (unsigned_a_i),
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.unsigned_b (unsigned_b_i),
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.subtract (subtract_i)
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);
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endmodule
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module dsp_t1_10x9x32_cfg_params (
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input [ 9:0] a_i,
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input [ 8:0] b_i,
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input [ 5:0] acc_fir_i,
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output [18:0] z_o,
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output [ 8:0] dly_b_o,
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(* clkbuf_sink *)
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input clock_i,
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input reset_i,
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input [2:0] feedback_i,
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input load_acc_i,
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input unsigned_a_i,
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input unsigned_b_i,
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input subtract_i
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);
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parameter [9:0] COEFF_0 = 10'd0;
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parameter [9:0] COEFF_1 = 10'd0;
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parameter [9:0] COEFF_2 = 10'd0;
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parameter [9:0] COEFF_3 = 10'd0;
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parameter [2:0] OUTPUT_SELECT = 3'd0;
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parameter [0:0] SATURATE_ENABLE = 1'd0;
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parameter [5:0] SHIFT_RIGHT = 6'd0;
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parameter [0:0] ROUND = 1'd0;
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parameter [0:0] REGISTER_INPUTS = 1'd0;
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wire [37:0] z;
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wire [17:0] dly_b;
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QL_DSP3 # (
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.MODE_BITS ({
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REGISTER_INPUTS,
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ROUND,
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SHIFT_RIGHT,
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SATURATE_ENABLE,
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OUTPUT_SELECT,
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1'b1, // Fractured
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10'd0, COEFF_3,
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10'd0, COEFF_2,
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10'd0, COEFF_1,
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10'd0, COEFF_0
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})
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) _TECHMAP_REPLACE_ (
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.a ({10'd0, a_i}),
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.b ({ 9'd0, b_i}),
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.acc_fir (acc_fir_i),
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.z (z),
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.dly_b (dly_b),
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.clk (clock_i),
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.reset (reset_i),
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.feedback (feedback_i),
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.load_acc (load_acc_i),
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.unsigned_a (unsigned_a_i),
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.unsigned_b (unsigned_b_i),
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.subtract (subtract_i)
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);
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assign z_o = z[18:0];
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assign dly_b_o = dly_b_o[8:0];
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endmodule
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