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yosys/frontends/verilog
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Clifford Wolf 9804c86e87 Add approximate support for SV "var" keyword, fixes #987 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 07:52:51 +02:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
const2ast.cc Convert more log_error() to log_file_error() where possible. 2018-07-20 09:37:44 -07:00
Makefile.inc Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 2019-03-29 16:32:44 +01:00
preproc.cc Support SystemVerilog `` extension for macros 2018-05-17 00:09:56 -04:00
verilog_frontend.cc Include filename in "Executing Verilog-2005 frontend" message, fixes #959 2019-04-30 15:37:46 +02:00
verilog_frontend.h New behavior for front-end handling of whiteboxes 2019-04-20 22:24:50 +02:00
verilog_lexer.l Add approximate support for SV "var" keyword, fixes #987 2019-05-04 07:52:51 +02:00
verilog_parser.y Add approximate support for SV "var" keyword, fixes #987 2019-05-04 07:52:51 +02:00