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18 lines
365 B
Verilog
18 lines
365 B
Verilog
module \$__COUNT_ (CE, CLK, OUT, POUT, RST, UP);
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input wire CE;
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input wire CLK;
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output reg OUT;
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output reg[WIDTH-1:0] POUT;
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input wire RST;
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input wire UP;
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parameter COUNT_TO = 1;
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parameter RESET_MODE = "RISING";
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parameter RESET_TO_MAX = "1";
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parameter HAS_POUT = 0;
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parameter HAS_CE = 0;
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parameter WIDTH = 8;
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parameter DIRECTION = "DOWN";
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endmodule
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