mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
9 lines
125 B
Verilog
9 lines
125 B
Verilog
`include "common_sim.vh"
|
|
`include "ccu2d_sim.vh"
|
|
|
|
`ifndef NO_INCLUDES
|
|
|
|
`include "cells_ff.vh"
|
|
`include "cells_io.vh"
|
|
|
|
`endif
|