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yosys/techlibs
2026-05-22 18:39:42 +02:00
..
achronix
analogdevices
anlogic
common
coolrunner2
easic
efinix
fabulous
gatemate
gowin gowin: replace positional arguments in cells_sim.v with named 2026-05-22 18:39:42 +02:00
greenpak4
ice40 signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
intel intel: register bram celltypes 2026-05-22 18:39:42 +02:00
intel_alm intel: register bram celltypes 2026-05-22 18:39:42 +02:00
lattice
microchip
nanoxplore
quicklogic signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
sf2
xilinx signorm: disable in passes that use swap_names 2026-05-22 18:37:58 +02:00
.gitignore
fix_mod.py