mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-07 01:54:10 +00:00
96f64f4788
For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case. |
||
|---|---|---|
| .. | ||
| .gitignore | ||
| basic00.sv | ||
| basic01.sv | ||
| basic02.sv | ||
| basic03.sv | ||
| basic04.sv | ||
| basic04.vhd | ||
| basic05.sv | ||
| basic05.vhd | ||
| counter.sv | ||
| extnets.sv | ||
| Makefile | ||
| nested_clk_else.sv | ||
| runtest.sh | ||
| sva_not.sv | ||
| sva_range.sv | ||
| sva_throughout.sv | ||