Marcin Kościelnicki 7a9081440c xilinx: Add simulation models for MULT18X18* and DSP48A*. ... This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6)		2019-11-19 01:00:58 +01:00
..
tests
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
abc9_xc7.box
abc9_xc7.lut
abc9_xc7_nowide.lut
arith_map.v
brams_init.py
cells_map.v
cells_sim.v	xilinx: Add simulation models for MULT18X18* and DSP48A*.	2019-11-19 01:00:58 +01:00
cells_xtra.py	xilinx: Add simulation models for MULT18X18* and DSP48A*.	2019-11-19 01:00:58 +01:00
cells_xtra.v	xilinx: Add simulation models for MULT18X18* and DSP48A*.	2019-11-19 01:00:58 +01:00
lut_map.v
lutrams.txt
lutrams_map.v
Makefile.inc
mux_map.v
synth_xilinx.cc
xc3s_mult_map.v
xc3sda_dsp_map.v
xc4v_dsp_map.v
xc5v_dsp_map.v
xc6s_brams.txt
xc6s_brams_map.v
xc6s_dsp_map.v
xc6s_ff_map.v
xc7_brams_map.v
xc7_dsp_map.v
xc7_ff_map.v
xc7_xcu_brams.txt
xcu_brams_map.v
xcu_dsp_map.v
xcup_urams.txt
xcup_urams_map.v