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84 lines
2.1 KiB
Verilog
84 lines
2.1 KiB
Verilog
// Signed 40-bit streaming accumulator with 16-bit inputs
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// File: HDL_Coding_Techniques/multipliers/multipliers4.v
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//
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// Source:
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// https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug901-vivado-synthesis.pdf p.90
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//
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module macc # (parameter SIZEIN = 16, SIZEOUT = 40) (
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input clk, ce, sload,
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input signed [SIZEIN-1:0] a, b,
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output signed [SIZEOUT-1:0] accum_out
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);
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// Declare registers for intermediate values
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reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0;
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reg sload_reg = 0;
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reg signed [2*SIZEIN-1:0] mult_reg = 0;
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reg signed [SIZEOUT-1:0] adder_out = 0, old_result;
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always @* /*(adder_out or sload_reg)*/ begin // Modification necessary to fix sim/synth mismatch
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if (sload_reg)
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old_result <= 0;
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else
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// 'sload' is now active (=low) and opens the accumulation loop.
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// The accumulator takes the next multiplier output in
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// the same cycle.
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old_result <= adder_out;
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end
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always @(posedge clk)
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if (ce)
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begin
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a_reg <= a;
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b_reg <= b;
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mult_reg <= a_reg * b_reg;
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sload_reg <= sload;
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// Store accumulation result into a register
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adder_out <= old_result + mult_reg;
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end
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// Output accumulation result
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assign accum_out = adder_out;
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endmodule
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// Adapted variant of above
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module macc2 # (parameter SIZEIN = 16, SIZEOUT = 40) (
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input clk,
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input ce,
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input rst,
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input signed [SIZEIN-1:0] a, b,
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output signed [SIZEOUT-1:0] accum_out,
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output overflow
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);
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// Declare registers for intermediate values
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reg signed [SIZEIN-1:0] a_reg = 0, b_reg = 0, a_reg2 = 0, b_reg2 = 0;
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reg signed [2*SIZEIN-1:0] mult_reg = 0;
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reg signed [SIZEOUT:0] adder_out = 0;
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reg overflow_reg = 0;
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always @(posedge clk) begin
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//if (ce)
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begin
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a_reg <= a;
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b_reg <= b;
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a_reg2 <= a_reg;
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b_reg2 <= b_reg;
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mult_reg <= a_reg2 * b_reg2;
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// Store accumulation result into a register
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adder_out <= adder_out + mult_reg;
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overflow_reg <= overflow;
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end
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if (rst) begin
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a_reg <= 0;
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a_reg2 <= 0;
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b_reg <= 0;
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b_reg2 <= 0;
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mult_reg <= 0;
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adder_out <= 0;
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overflow_reg <= 1'b0;
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end
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end
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assign overflow = (adder_out >= 2**(SIZEOUT-1)) | overflow_reg;
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// Output accumulation result
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assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out;
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endmodule
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