mirror of
https://github.com/YosysHQ/yosys
synced 2025-11-04 05:19:11 +00:00
8 lines
134 B
Verilog
8 lines
134 B
Verilog
module tristate(en, i, o);
|
|
input en;
|
|
input i;
|
|
output reg o;
|
|
|
|
always @(en or i)
|
|
o <= (en)? i : 1'bZ;
|
|
endmodule
|