Akash Levy 71586d39b0 Merge from upstream		2025-11-12 08:14:33 -08:00
..
aiger
alumacc	Run toposort in both directions for better results	2025-09-09 07:45:25 -07:00
arch	Merge from upstream	2025-11-12 08:14:33 -08:00
asicworld
bind
blif
bram
bugpoint	raise_error: don't rely on module ordering in test	2025-09-16 15:47:16 +02:00
cxxrtl	tests: replace CC and gcc with CXX and g++	2025-09-11 16:50:23 +02:00
errors
fmt	tests: replace CC and gcc with CXX and g++	2025-09-11 16:50:23 +02:00
fsm
functional	read_verilog: add -relativeshare for synthesis reproducibility testing	2025-09-16 15:47:35 +02:00
hana
liberty	libparse: fix quoting and negedge in filterlib -verilogsim	2025-11-05 14:13:58 +01:00
lut
memfile
memlib
memories
opt	Merge remote-tracking branch 'donn/pyosys_bugfixes' into merge_pybind11	2025-10-26 02:39:43 +03:00
opt_share
peepopt	Smallfix	2025-09-30 14:18:23 -07:00
proc
pyosys	pyosys: fix regressions from 0.58	2025-10-26 02:21:40 +03:00
realmath
rpc
rtlil	Add CONST_FLAG_UNSIZED	2025-11-07 17:45:07 +13:00
sat	fix(parse): #5234 adjust width of rhs according to lhs	2025-09-16 15:24:23 +02:00
select
share
silimate	Update fanoutbuf	2025-10-01 20:59:36 -07:00
sim	Revert sim's cycle_width default back to 10, but keep -width option	2025-10-20 14:40:05 +02:00
simple
simple_abc9
smv
sva
svinterfaces	tests/svinterfaces: re-chmod test script	2025-10-15 09:49:53 +13:00
svtypes	Merge upstream in	2025-09-09 05:50:48 -07:00
techmap	Baseline	2025-11-06 06:44:35 -08:00
tools	tests: replace CC and gcc with CXX and g++	2025-09-11 16:50:23 +02:00
unit	Optimize IdString operations to avoid calling c_str()	2025-11-12 11:52:04 +01:00
various	Merge branch 'YosysHQ:main' into main	2025-11-05 15:40:09 -05:00
verific	Merge branch 'YosysHQ:main' into main	2025-11-03 13:38:04 -05:00
verilog	Merge pull request #5473 from YosysHQ/krys/unsized_params	2025-11-12 07:14:44 +13:00
vloghtb
xprop
.gitignore
gen-tests-makefile.sh