mirror of
https://github.com/YosysHQ/yosys
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55dc5a4e4f
* xilinx: add SCC test for DSP48E1 * xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1 Have a test that checks it works through ABC9 when enabled * abc9 to break SCCs using $__ABC9_SCC_BREAKER module * Add test * abc9_ops: remove refs to (* abc9_keep *) on wires * abc9_ops: do not bypass cells in an SCC * Add myself to CODEOWNERS for abc9* * Fix compile * abc9_ops: run -prep_hier before scc * Fix tests * Remove bug reference pending fix * abc9: fix for -prep_hier -dff * xaiger: restore PI handling * abc9_ops: -prep_xaiger sigmap * abc9_ops: -mark_scc -> -break_scc * abc9: eliminate hard-coded abc9.box from tests Also tidy up * Address review
43 lines
1.4 KiB
Text
43 lines
1.4 KiB
Text
## CODE NOTIFICATIONS
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# Register yourself here to be notified about modifications
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# for any files you have an interest in/know your way around.
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# Each line is a file pattern followed by one or more users.
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# Both github usernames and email addresses are supported.
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# Order is important; the last matching pattern takes the most
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# precedence. Previous matches will not be applied.
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# PATH (can use glob) USERNAME(S)
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passes/cmds/scratchpad.cc @nakengelhardt
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frontends/rpc/ @whitequark
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backends/cxxrtl/ @whitequark
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passes/cmds/bugpoint.cc @whitequark
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passes/techmap/flowmap.cc @whitequark
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passes/opt/opt_lut.cc @whitequark
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passes/techmap/abc9*.cc @eddiehung
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backends/aiger/xaiger.cc @eddiehung
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## External Contributors
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# Only users with write permission to the repository get review
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# requests automatically, but we add information for other
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# contributors here too, so we know who to ask to take a look.
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# These still override previous lines, so be careful not to
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# accidentally disable any of the above rules.
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frontends/verilog/ @zachjs
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frontends/ast/ @zachjs
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techlibs/intel_alm/ @ZirconiumX
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# pyosys
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misc/*.py @btut
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backends/firrtl @ucbjrl @azidar
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passes/sat/qbfsat.cc @boqwxp
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passes/sat/qbfsat.h @boqwxp
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passes/cmds/exec.cc @boqwxp
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passes/cmds/printattrs.cc @boqwxp
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