Catherine cb07710162 write_verilog: only warn on processes with sync rules. ... Processes without sync rules correspond to simple decision trees that directly correspond to `always @*` or `always_comb` blocks in Verilog, and do not need a warning. This removes the need to suppress warnings during the RTLIL-to-Verilog conversion performed by Amaranth.		2024-04-02 14:48:44 +01:00
..
aiger	write_aiger: Include $assert and $assume cells in -ywmap output	2024-03-04 16:53:03 +01:00
blif	Ignore $scopeinfo in write_blif	2024-02-06 17:51:29 +01:00
btor	tests: use /usr/bin/env for bash.	2023-08-12 11:59:39 +10:00
cxxrtl	fmt: if enabled, group padding zeroes.	2024-04-02 12:13:22 +02:00
edif	Ignore $scopeinfo in write_edif	2024-02-06 17:51:29 +01:00
firrtl	Ignore $scopeinfo in write_firrtl	2024-02-06 17:51:29 +01:00
intersynth	Intersynth URL	2021-06-09 12:42:52 +02:00
jny	chore: fix master branch refs	2024-03-24 00:41:54 -04:00
json	Ignore $scopeinfo in write_json	2024-02-06 17:51:29 +01:00
rtlil	backends/rtlil: Do not shorten a value with z bits to 'x	2023-01-29 14:02:25 +01:00
simplec	tests: use /usr/bin/env for bash.	2023-08-12 11:59:39 +10:00
smt2	smtbmc: Add --track-assumes and --minimize-assumes options	2024-03-11 15:13:11 +01:00
smv	Ignore $scopeinfo in write_smv	2024-02-06 17:51:29 +01:00
spice	Ignore $scopeinfo in write_spice	2024-02-06 17:51:29 +01:00
table	Fixing old e-mail addresses and deadnames	2021-06-08 00:39:36 +02:00
verilog	write_verilog: only warn on processes with sync rules.	2024-04-02 14:48:44 +01:00