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yosys/techlibs/ice40
2016-02-07 11:19:48 +01:00
..
tests
.gitignore
arith_map.v
brams.txt
brams_init.py
brams_map.v
cells_map.v
cells_sim.v Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
ice40_ffinit.cc
ice40_ffssr.cc
ice40_opt.cc
Makefile.inc
synth_ice40.cc