yosys/tests/hana/test_simulation_sop_basic_8_test.v at 94744ac7b0238048869f04ea36cc35314798a70b - mirrors/yosys - Libre-Chip.org

mirrors/yosys

mirror of https://github.com/YosysHQ/yosys synced 2025-04-25 10:05:33 +00:00

Clifford Wolf 7764d0ba1d initial import

2013-01-05 11:13:26 +01:00

3 lines

54 B

Verilog

Raw Blame History

	`module test(output out);`
	`assign out = 1'b0;`
	`endmodule`