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yosys/techlibs/common
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
..
.gitignore
abc9_map.v
abc9_model.v
abc9_unmap.v
adff2dff.v
cellhelp.py
cells.lib
cmp2lcu.v
cmp2lut.v
dff2ff.v
gate2lut.v
gen_fine_ffs.py
Makefile.inc
mul2dsp.v
pmux2mux.v
prep.cc
simcells.v
simlib.v
synth.cc
techmap.v