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yosys/techlibs/ice40
Sylvain Munaut 3806b07303 ice40: Fix typo in SB_CARRY specify for LP/UltraPlus
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
2021-08-17 14:33:30 +02:00
..
tests
.gitignore
abc9_model.v Fix icestorm links 2021-06-09 12:39:12 +02:00
arith_map.v Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
brams.txt
brams_init.py
brams_map.v verilog: significant block scoping improvements 2021-01-31 09:42:09 -05:00
cells_map.v Add force_downto and force_upto wire attributes. 2020-05-19 01:42:40 +02:00
cells_sim.v ice40: Fix typo in SB_CARRY specify for LP/UltraPlus 2021-08-17 14:33:30 +02:00
dsp_map.v
ff_map.v ice40: Use dfflegalize. 2020-07-05 05:12:09 +02:00
ice40_braminit.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
ice40_opt.cc Fixing old e-mail addresses and deadnames 2021-06-08 00:39:36 +02:00
latches_map.v
Makefile.inc synth_ice40: Use opt_dff. 2020-07-30 22:26:20 +02:00
synth_ice40.cc opt_lut: Allow more than one -dlogic per cell type. 2021-07-29 17:30:07 +02:00