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14 lines
476 B
Text
14 lines
476 B
Text
# division by constants should not infer carry chains.
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read_verilog <<EOF
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module top (input [15:0] a, output [15:0] y);
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assign y = a / 3;
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endmodule
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EOF
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equiv_opt -assert -map +/quicklogic/qlf_k6n10f/cells_sim.v synth_quicklogic -family qlf_k6n10f
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-max 100 t:$lut
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select -assert-none t:$lut %% t:* %D
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